CMLT3410 npn cmlt7410 pnp cmlt3474 npn/pnp surface mount silicon dual, low v ce(sat) transistors description: these central semiconductor dual devices are low v ce(sat) silicon transistors in an sot-563 surface mount package designed for small signal general purpose amplifier and switching applications requiring low collector emitter saturation voltage. marking codes: CMLT3410: c34 cmlt7410: c74 cmlt3474: c37 maximum ratings: (t a =25c) symbol units collector-base voltage v cbo 40 v collector-emitter voltage v ceo 25 v emitter-base voltage v ebo 6.0 v continuous collector current i c 1.0 a peak collector current i cm 1.5 a power dissipation p d 350 mw operating and storage junction temperature t j , t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) npn pnp symbol test conditions min typ typ max units i cbo v cb =40v 100 na i ebo v eb =6.0v 100 na bv cbo i c =100a 40 v bv ceo i c =10ma 25 v bv ebo i e =100a 6.0 v v ce(sat) i c =50ma, i b =5.0ma 25 30 50 mv v ce(sat) i c =100ma, i b =10ma 40 50 75 mv v ce(sat) i c =200ma, i b =20ma 80 95 150 mv v ce(sat) i c =500ma, i b =50ma 190 205 250 mv v ce(sat) i c =800ma, i b =80ma 290 320 400 mv v ce(sat) i c =1.0a, i b =100ma 360 400 450 mv v be(sat) i c =800ma, i b =80ma 1.1 v v be(on) v ce =1.0v, i c =10ma 0.9 v h fe v ce =1.0v, i c =10ma 100 h fe v ce =1.0v, i c =100ma 100 300 h fe v ce =1.0v, i c =500ma 100 h fe v ce =1.0v, i c =1.0a 50 f t v ce =10v, i c =50ma, f=100mhz 100 mhz c ob v cb =10v, i e =0, f=1.0mhz (CMLT3410) 6.0 10 pf c ob v cb =10v, i e =0, f=1.0mhz (cmlt7410) 10 15 pf sot-563 case r5 (29-june 2015) www.centralsemi.com
sot-563 case - mechanical outline lead code: 1) emitter q1 2) base q1 3) collector q2 4) emitter q2 5) base q2 6) collector q1 marking code: CMLT3410: c34 marking code: cmlt7410: c74 marking code: cmlt3474: c37 pin configurations CMLT3410 npn cmlt7410 pnp cmlt3474 npn/pnp surface mount silicon dual, low v ce(sat) transistors www.centralsemi.com r5 (29-june 2015)
CMLT3410 npn cmlt7410 pnp cmlt3474 npn/pnp surface mount silicon dual, low v ce(sat) transistors services ? bonded inventory ? custom electrical screening ? custom electrical characteristic curves ? spice models ? custom packaging ? package base options ? custom device development / multi discrete modules (mdm?) ? bare die available for hybrid applications limitations and damages disclaimer: in no event shall central be liable for any collateral, indirect, punitive, incidental, consequential, or exemplary damages in connection with or arising out of a purchase order or contract or the use of products provided hereunder, regardless of whether central has been advised of the possibility of such damages. excluded damages shall include, but not be restricted to: cost of removal or reinstallation, rework, ancillary costs to the procurement of substitute products, loss of profits, loss of savings, loss of use, loss of data, or business interruption. no claim, suit, or action shall be brought against central more than two (2) years after the related cause of action has occurred. in no event shall centrals aggregate liability from any warranty, indemnity, or other obligation arising out of or in connection with a purchase order or contract, or any use of any central product provided hereunder, exceed the total amount paid to central for the specific products sold under a purchase order or contract with respect to which losses or damages are claimed. the existence of more than one (1) claim against the specific products sold to buyer under a purchase order or contract shall not enlarge or extend this limit. buyer understands and agrees that the foregoing liability limitations are essential elements of a purchase order or contract and that in the absence of such limitations, the material and economic terms of the purchase order or contract would be substantially different. www.centralsemi.com r5 (29-june 2015)
|
